As the density of semiconductor devices continues to increase, the need for smaller interconnections also increases. Historically, the semiconductor industry has used a subtractive etching process to pattern metal interconnect layers of the semiconductor. This metal processing technique, however, has limitations including poor step coverage, non-planarity, shorts and other fabrication problems. To address these problems, a dual damascene technique has been developed. This process, as explained in "Dual Damascene: A ULSI Wiring Technology", Kaanta et al., 1991 VMIC Conference, 144-150 (Jun. 11-12, 1991) and incorporated herein by reference, involves the deposition of a metal into contact vias and conductor trenches which are patterned in the semiconductor. The semiconductor is then subjected to a known CMP (chemically-mechanically polish) process to both planarize the semiconductor and remove excess metal from all but the patterned areas.
The metal layer can be fabricated using known CVD (chemical vapor deposition) or PVD (physical vapor deposition) techniques. The metal interconnects are typically an aluminum alloys containing dopants, such as silicon and copper. These dopants are Si and Cu precipitates which tend to migrate to the grain boundaries of the aluminum during deposition. The precipitates are harder than aluminum. Thus, they are hard to dissolve and remove during the CMP process. The precipitates also contribute to defects in the aluminum, such as scratches, which materialize during the CMP process. These problems are present in all CMP processes, and not limited to removing metal alloys used in a dual damascene process.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a process of fabricating metal alloy interconnects in an integrated circuit which improves a CMP process and reduces defects experienced during CMP.